The present disclosure relates to an electric circuit, more particularly, to a power-on reset circuit.
When an electronic device is powered up, a supply voltage VDD for the electronic device rises from zero voltage to a pre-defined voltage (e.g. 3.3V). During this period, logic states of internal latches or flip-flops in the electronic device are un-known because they may carry logic memories from previous logic states. Un-known internal logic states can cause unpredictable behaviors in the electronic device and prevent the electronic device from performing its intended functions. A power-on-reset (POR) circuit can provide reset signals to reset internal latches or flip-flops to well-defined logic states during a power-on period, thus ensuring the proper functions of the electronic device.
A conventional POR circuit 100, as shown in FIG. 1, can include a Schmitt trigger circuit 110 consisting of transistors P2/P3/N2/N3, a stabilization capacitor CO, a current source PMOS transistor P1, a resistor divider consisting of resistors R1 and R2, and an NMOS transistor N1. An output signal can be produced at a node PORB for resetting internal logics in an electronic device. The PMOS transistor P1 can provide source current from VDD to the resistor divider. The NMOS transistor N1 can produce a trigger signal at the node S2 for the Schmitt trigger circuit 110. The Schmitt trigger circuit 110 can bypass voltage fluctuations and clamp the voltage of the output node PORB during powers up. The PORB node is initially at ground voltage (which can be defined as zero voltage).
During power on, VDD rises from ground voltage to a pre-defined voltage, say 3.3V. The gate node of PMOS transistor P1 and the gate node of PMOS transistor P2 are both at zero voltage, thus they are both turned on. The current flows through P1 can produce a voltage at the node S1 as defined by VIN×R2/(R1+R2) where VIN is the drain voltage of P1. The current flows through P2 can cause the voltage at S2 to follow the rise of the voltage supply VDD. The node S2 has a higher voltage than the node S1 as S1 is resistive divided by VDD. NMOS transistor N3 can therefore turn on once the voltage at the node S2 reaches its threshold turn-on voltage. When N3 is turned on, the node PORB is further clamped to zero voltage. When VDD rises up further to reach the threshold turn-on voltage of NMOS transistor N1, N1 is turned on and pulls the node S2 low. At that moment, P2 is already turned on and therefore P2/N1 forms a resistive divider at the node S2. If N1 is made much larger than P2, then the pulling effect to the node S2 is much stronger at N1, the node S2 can be easily pulled to zero voltage, which can shut off the N3 and turns on P3. As a result, the PORB node changes from logic low to logic high. Subsequently P2 is shut off and N2 is turned on by the high logic level at the node PORB.P1 is also shut off, thus preventing direct DC current from flowing through the resistive divider and minimizing power consumption.
A significant drawback associated with the conventional POR circuit 100 is that it may not provide reliable reset signals if VDD has not dropped to zero voltage before the next powers up.
FIG. 2A shows the waveform for a proper power cycling sequence. When VDD rises from zero voltage, PORB changes from logic low to logic high after a predetermined time T1. When VDD reaches VTH1, S1 reaches the turn-on threshold of N1; PORB steps up and then follows VDD until VDD reaches to its stable value VDD_f. Td1 is defined as the time during which PORB follows VDD to rise to VDD_f. The period between 0 and T1+Td1 can be called “power on” or “power up”.
VDD remains at the VDD_f from T1+Td1 to T2. After T2, the electronic device powers off. VDD decreases following a typical exponential decay curve for an RC circuit. The rate of decrease is fast at the beginning (from time T2 to T2+Td2) and then slows down when it reaches to a low voltage level VTH2 (typically around the parasitic diode voltage). Therefore, the period from T2 to T3 can be very long period. If the next power on occurs long enough after the last power off, the next power-on can be properly reset by the POR circuit, as shown in FIG. 2A.
If the next power-on event occurs shortly after the previous power cycle, the next power-on may not be properly reset by the POR circuit. As shown in FIG. 2B, because of the short period of T3−T2, VDD does not have enough time to drop to zero voltage when the next power-on event begins at T3, PORB closely follows VDD. Let us assume VDD and PORB drop to around ˜0.6V=VTH2. VDD suddenly rises up again at time T3. At this time, as can be seen in FIG. 1, the gate voltages of PMOS transistors P1/P2 and VDD are at 0.6V. The transistors P1/P2 are therefore shut off. The node S2 is clamped to zero voltage from the previous power-up sequence. Because P2 shuts off, it cannot pull up the node S2 to logic high as in a normal power-on cycle. P1 shuts off and S1 is at zero voltage, thus N1 being held in an off state. S2 is also at zero voltage. P3 is therefore completely turned on and PORB closely follows VDD in the next power-on cycle. In this example, the POR circuit 100 completely fails to produce a reset signal in the second power-on cycle.
There is therefore a need for a POR circuit to perform proper reset functions for fast power cycles. Moreover, it is desirable to eliminate DC current leakage and minimize VDD fluctuations during power-on of a POR circuit.